International Journals (*corresponding)

94. S. Lee, S. Eom, J. Jeong, J. Lee, S. Lee, H. Yun, Y. Ahn, and R.-H. Baek*, "Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs with Multiple Structural Variations," IEEE ACCESS, vol. 12, 184619-184628, Dec. 2024. [link]

93. S. Eom, S. Lee, H. Yun, K. Cho, S. Kim, and R.-H. Baek*, "Machine Learning-Driven Extraction of Hybrid Compact Models Integrating Neural Networks and Berkeley Short-Channel Insulated-Gate Field-Effect Transistor Model-Common Multigate for Multidevice Applications," Advanced Intelligent Systems, 2400571, Nov. 2024. [link]

92. S. Lee, J. Jeong, and R.-H. Baek*, "Channel Trimming Process to Improve Electro-Thermal Characteristics for Sub-3-nm Node Si Nanosheet FETs" IEEE Trans. on Electron Devices, Vol: 71, Issue: 11, Nov. 2024. [link]

91. K. Nam, D. Kim, H. Yun, C. Park, H. Jang, K. Cho, S.Eom, J. Kim, S. Lee, N. Lee, G. Kim, and R.-H. Baek*, "Program Pulse Control for Program Efficiency and Disturbance of 3D-NAND Flash Using Novel Machine Learning-Based Pareto Optimization," IEEE Trans. on Electron Devices, Vol: 71, Issue: 11, Nov. 2024. [link]

90. H. Yun, H. Jang, S. Lee, J. Lee,  K. Cho, S. Eom, S. Kim, C.-K. Kim, H.-C. Byun, S. Han, M.-S. Yoo, and R.-H. Baek*, "Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring," Advanced Intelligent Systems, 2300920, Sep. 2024. [link]

89. B. Kang, J. An, J. Park, G. Hong, B. Ham, S.-M. Ahn, and R.-H. Baek*, "FEOL Monolithic Co-integration of FeFET and CMOS on 8-inch Wafer Using Laser Spike Annealing with Implementation of a FeFET Inverter," IEEE Access, vol. 12, 110273-110282, Aug. 2024. [link]

88. D. Kim, K. Nam, C. Park, H. You, Y. Kim, S. Park, and R.-H. Baek*, "Impact of Process Sequence and Device Architecture on Mechanical Stress and Electrical Properties of 3D NAND Flash," IEEE Trans. on Electron Devices, Vol: 71, Issue: 9, Jul. 2024. [link]

87. J. Lee, S. Song, and R.-H. Baek*, "BS-PDN Implemented the Latest Logic Devices for 14 Angstrom Technology Node",  IEEE Trans. on Electron Devices, Vol: 71, Issue: 7, Jul. 2024. [link] 

86. K. Cho, C. Park, H. Jang, H. Yun, S. Eom, M. Park, and R.-H. Baek*, "Neural Network-Based Prediction for Cross-Temperature Induced shift in 3D NAND Flash Memory," Solid-State Electronics, vol. 217, 108925, Jul. 2024. [link] 

85. J. Jeong, S. Lee, and R.-H. Baek*, "Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for controlling Parasitic Bottom Transistors," Nanomaterials, vol. 14(12), 1006, Jun. 2024. [link]

84. D. Kim, K. Nam, C. Park, H. You, M. Park, Y. Kim, S. Park, and R.-H. Baek*, "Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory," Solid-State Electronics, vol. 216, 108927, Jun. 2024. [link] 

83. B. Kang, S.-M. Ahn, J. Park, J. An, G. Hong, B. Ham, and R.-H. Baek*, "BCl3/Cl2 Plasma Etching Process to Fabricate a Ferroelectric Gate Structure for Device Integration," Solid-State Electronics, vol. 216, 108918, Jun. 2024. [link] 

82. S. Eom, H. Yun, H. Jang, K. Cho, S. Lee, J. Jeong, and R.-H. Baek*, "Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation," Advanced Intelligent Systems, 2300435, Jan. 2024. [link]

81. J. Park, J. Kim, S. Lee, G. Kim, N. Lee, R.-H.Baek, D. Kim, C. Kim, M. Kang, and Y. Kim*, "Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning," IEEE Access, vol. 12, 23881-23886, Jan. 2024. [link]

80. H. You, K. Nam, J. An, C. Park, D. Kim, S. Lee, N. Lee, and R. -H. Baek*, "Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications," IEEE Access, vol. 12, 10988-10994, Jan. 2024. [link]

International Journals (*corresponding)

79. S. Lee, J. Jeong, J. Lee, S. Lee, J. Lim, Y. Ahn, and R. -H. Baek*, "Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors," IEEE Trans. on Electron Devices, Vol: 70, Issue: 12, Dec. 2023. [link] 

78. J. Lim, J. Jeong, J. Lee, S. Lee, S. Lee, Y. Ahn, and R. -H. Baek*, "Investigation of Electro-thermal Characteristics in Silicon Forksheet FETs for Sub-3-nm Node," IEEE Trans. on Electron Devices, Vol: 70, Issue:12, Dec. 2023. [link] 

77. K. Cho, J. -S. Lee, C. Park, H. Yun, H. Jang, S. Eom, M. S. Park, H. -C. Choi, and R. -H. Baek*, "Modeling of 3D NAND Characteristics for Cross-Temperature by using Graph Neural Network and Its Application," Advanced Intelligent Systems, 2300400, Dec. 2023. [link] 

76. K. Nam, C. Park, D. Kim, S. Lee, N. Lee and, R. -H. Baek*, "Bidirectional Precharge and Negative Bias Scheme for Program Disturbance Suppression in 3-D NAND Flash Memory," IEEE Trans. on Electron Devices, Vol: 70, Issue: 12, Dec. 2023. [link]

75. H. Jang, K. Nam, H. Yun, K. Cho, S. Eom, M. S. Park, and R.-H. Baek*, "Optimization of Process Parameters on Short-Term Retention for Charge-Trapping 3-D NAND Flash Memories Using Novel Neural Networks Approach," IEEE Trans. on Electron Devices, Vol: 70, Issue: 8, Aug. 2023. [link]

74. H. Yun, C.-H. An, H. Jang, K. Cho, J.-S. Lee, S. Eom, C.-K. Kim, M.-S. Yoo, H.-C. Choi, and R.-H. Baek*, "Accurate Prediction and Reliable Parameter Optimization of Neural Network for Process-Monitoring and Technology Development," Advanced Intelligent Systems, 2300089, Jul. 2023. [link]

73. K. Cho, H. Yun, K. Nam, C. Park, H. Jang, J.-S. Yoon, H.-C. Choi, M. S. Park, and R.-H. Baek*, “Enhancement of ISPP Efficiency Using Neural Network-based Optimization of 3D NAND Cell,” IEEE Trans. on Electron Devices, vol. 70, no. 7, 3504-3510,  Jul. 2023. [link] 

72. J. Park, K.-K. Choi, J. H. An, B. Kang, H. You, G. Hong, S.-M. Ahn, and R.-H. Baek*, "Curing Process on Passivation Layer for Backside-Illuminated CMOS Image Sensor Application,"  IEEE Access, vol. 11, 60660-60667, Jun. 2023. [link]

71. C. Park, J.-S. Yoon, K. Nam, H. Jang, and R.-H. Baek*, “Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps,” Nanomaterials, vol. 13(9), 1341, Apr. 2023. [link]

70. G. Yang, C. Park, K. Nam, D. Kim, M. S. Park, and R.-H. Baek*, “Improved ISPP scheme for narrow threshold voltage distribution in 3-D NAND flash memory,” Solid-State Electronics, vol. 202, 108607, Apr. 2023. [link]

69. C. Park, J.-S. Yoon, K. Nam, H. Jang, M. Park, and R.-H. Baek*, "Quantitative analysis of irregular channel shape effects on charge-trapping efficiency using massive 3D NAND data," Materials Science in Semiconductor Processing (MSSP), vol. 157, 107333, Apr. 2023. [link]

68. S. Lee, J. Jeong, B. Kang, S. Lee, J. Lee, J. Lim, H.-J. Hwang, S.-M. Ahn, and R.-H. Baek*, "A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs," Nanomaterials, vol. 13(5), 868, Mar. 2023. [link]

67. J. Lee, S. Heo, H. Hwang, and R.-H. Baek*, "Novel High-Speed Ternary Logic Using Step-Shaped Threshold Switch," IEEE Electron Device Letters, Vol. 44(3), pp. 368-371, Mar. 2023. [link]

66. J. An, K.-K. Choi, J. Park, B. Kang, H. You, S.-M. Ahn, and R.-H. Baek*, "H2 Plasma and PMA Effects on PEALD-Al2O3 Films with Different O2 Plasma Exposure Times for CIS Passivation Layers," Nanomaterials, vol. 13(4), 731, Feb. 2023. [link]

65. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek*, "Novel Trench Inner-Spacer Scheme to Eliminate Parasitic Bottom Transistors in Silicon Nanosheet FETs," IEEE Trans. on Electron Devices, vol. 152(2), pp. 396-401, Feb. 2023. [link]

64. K. Nam, C. Park, H. Yun, J.-S. Yoon, H. Jang, K. Cho, M. Park, H.-C. Choi, and R.-H. Baek*, "Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning," IEEE ACCESS, vol. 11, pp. 7135-7144, Jan. 2023. [link]

International Journals (*corresponding)

63. J. An, K.-K. Choi, B. Kang, and R.-H. Baek*, "Curing defects in plasma-enhanced atomic layer deposition of Al2O3 by six methods", Materials Science in Semiconductor Processing (MSSP), vol. 152, 107070, Dec. 2022. [link]

62. H. Lee, R.-H. Baek, H.-C. Choi*, "Learning-Based Ordering Characters on Ancient Document", Computational Intelligence and Neuroscience, vol. 2022, pp. 1-15, Nov. 2022. [link]

61. J. Lee, J.-S. Yoon, J. Lim, and R.-H. Baek*, "Electrical Coupling Effect of Forksheet FET for Power, Performance, and Area Analysis", IEEE Trans. on Electron Devices, Vol. 69(12), pp. 7096-7101, Oct. 2022. [link]

60. S. Lee, J.-S. Yoon, and R.-H. Baek*, "Nanowire Diameter Dependency of the Variability in n/p Silicon Nanowire FETs With UltrashortGate Length of 15 nm", IEEE Trans. on Electron Devices, vol. 69(12), pp. 6529-6534, Oct. 2022. [link]

59. S. Lee, J. Jeong, J.-S. Yoon, S. Lee, J. Lee, J. Lim, and R.-H. Baek*, "Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors", Nanomaterials, vol. 12(19), 3349, Sep. 2022. [link]

58.  U. Ullah, J.-S. Lee, C.-H. An, H. Lee, S.-Y. Park, R.-H. Baek, and H.-C. Choi, "A Review of Multi-Modal Learning from the Text-Guided Visual Processing Viewpoint", Sensors, vol. 22(18), 6816, Sep. 2022. [link]

57. H. Jang, C. Park, K. Nam, H. Yun, K. Cho, J.-S. Yoon, H.-C. Choi, H.-J. Kang, M. Park, J. Sim, and R.-H. Baek*, "Bi-Directional Long Short-Term Memory Neural Network Modeling of Data Retention Characterization in 3-D Triple-Level Cell NAND Flash Memory", IEEE Trans. on Electron Devices, vol. 69(8), pp. 4241 - 4247, Aug. 2022. [link]

56. K. Nam, C. Park, J.-S. Yoon, G. Yang, M.S. Park, and R.-H. Baek*, "Channel Thickness and Grain Size Engineering for Improvement of Variability and Performance in 3-D NAND Flash Memory", IEEE Trans. on Electron Devices, vol. 69(7), pp. 3681-3687, Jul. 2022. [link]

55. H. Jang, H. Yun, C. Park, K. Cho, K. Nam, J.-S. Yoon, H.-C. Choi*, and R.-H. Baek*, "Extraction of Device Structural Parameters Through DC/AC Performance Using an MLP Neural Network Algorithm", IEEE Access, vol. 10, pp. 64408 - 64419, Jun. 2022. [link]

54. K. Nam, C. Park, J.-S. Yoon, H. Yun, H. Jang, K. Cho, H.-J. Kang, M.S. Park, J. Sim, H.-C. Choi, and R.-H. Baek*, "Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using a Machine-Learning Method", Nanomaterials, vol. 12(11), 1808, Jun. 2022. [link]

53. S. Lee, J.-S. Yoon, J. Lee, J. Jeong, H. Yun, J. Lim, S. Lee, and R.-H. Baek*, "Novel Modeling Approach to Analyze Threshold Voltage Variability in Short Gate-Length (15–22 nm) Nanowire FETs with Various Channel Diameters", Nanomaterials, vol. 12(10), pp. 1721-1~9, May. 2022. [link]

52. Y.-J. Kim, R.-H. Baek, S. Chang, and K.-K. Choi*, "Effect of hydrogen plasma treatment on the electrical properties for SiC-based power MOSFETs", Microelectronics Engineering, vol. 258, 111769, Apr. 2022. [link]

51. J.-S. Lee, R.-H. Baek, and H.-C. Choi*, "Arbitrary Font Generation by Encoder Learning of Disentangled Features", Sensors, vol. 22(6), 2374, Mar. 2022. [link]

50. J.-S. Yoon, J. Jeong, S. Lee, J. Lee, S. Lee, R.-H. Baek*, and S.-K. Lim, "Performance, Power, and Area of Standard Cells in Sub 3 nm Node Using Buried Power Rail", IEEE Trans. on Electron Devices, vol. 69(3), pp. 894 - 899, Mar. 2022. [link]

49. J.-S. Yoon, J. Jeong, S. Lee, J. Lee, S. Lee, and R.-H. Baek*, "DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of sub-3nm Nanosheet Field-Effect Transistors", IEEE Access, vol. 10, pp. 22032 - 22037, Feb. 2022. [link]

International Journals (*corresponding)

48. J. Lee, J. -S. Yoon, J. Jeong, S. Lee, S. Lee, and R.-H. Baek*, "Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes", IEEE Access, vol. 9, pp.138192 - 138199,  Oct. 2021. [link]

47. B. Kang, K.-K. Choi, J. An, and R.-H. Baek*, "Demonstration of TiO2 Based Ultra High-k (k = 30) Metal-Insulator–Semiconductor Capacitor and Its Electrical Properties", Journal of Nanoscience and Nanotechnology, vol. 21, pp. 4394 - 4399, Aug. 2021. [link]

46. J. Lee, J. -S. Yoon, S. Lee, J. Jeong, and R.-H. Baek*, "TCAD-Based Flexible Fin Pitch Design for 3-nm Node 6T-SRAM Using Practical Source/Drain Patterning Scheme", IEEE Trans. on Electron Devices, vol. 68(3), pp. 1031 - 1036, Mar. 2021. [link]

45. J.-S. Yoon, S. Lee, H. Yun, and R.-H. Baek*, "Digital/Analog Performance Optimization of Vertical Nanowire FETs using Machine Learning", IEEE Access, vol. 9, pp. 29071 - 29077, Feb. 2021. [link]

44. K. Nam, C. Park, J.-S. Yoon, H. Jang, M. Park, J. Sim, and R.-H. Baek*, "Origin of Incremental Step Pulse Programming (ISPP) slope degradation in charge trap nitride based multi-layer 3D NAND flash", Solid-State Electronics, vol. 175, pp. 107930-1~6, Jan. 2021. (Most Downloaded SSE Articles in Jan. 2021) [link]

43. J. Jeong, J.-S. Yoon, and R.-H. Baek*, "Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs", IEEE Access, vol. 9, pp. 16728 - 16735, Jan. 2021. [link]

International Journals (*corresponding)

42. J.-S. Yoon and R.-H. Baek*, "Device Design Guideline of 5-nm-Node FinFETs and Nanosheet FETs for Analog/RF Applications", IEEE Access, vol. 8, pp. 189395 - 189403, Oct. 2020. [link]

41. J.-S. Yoon and R.-H. Baek*, "A Novel Sub-5-nm Node Dual-Workfunction Folded Cascode Nanosheet FETs for Low Power Mobile Applications", IEEE Access, vol. 8, pp. 196975 - 196978, Oct. 2020. [link]

40. H. Yun, J.-S. Yoon, J. Jeong, S. Lee,  H.-C. Choi, and R.-H. Baek*, "Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications", IEEE Journal of the Electron Device Society, vol. 8, pp. 1272 - 1280, Sep. 2020. [link]

39. H.-C. Choi, H. Yun, J.-S. Yoon, and R.-H. Baek*, "Neural Approach for Modeling and Optimizing Si-MOSFET Manufacturing", IEEE Access, vol. 8, pp. 159351 - 159370, Aug. 2020. [link]

38. J.-S. Yoon, S. Lee, J. Lee, J. Jeong, H. Yun, and R.-H. Baek*, "Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme", IEEE Trans. on Electron Devices, vol. 67, no.7, pp. 2732 - 2737, Jul. 2020. [link]

37. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek*, "Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application", IEEE Access, vol. 8, pp. 35873 - 35881, Feb. 2020. [link]

36. J. Jeong, J.-S. Yoon, S. Lee, and R.-H. Baek*, "Threshold Voltage Variations Induced by Si1−xGex and Si1−xCx of Sub 5-nm Node Silicon Nanosheet Field-Effect Transistors", Journal of Nanoscience and Nanotechnology, vol.20, no. 8, pp. 4684-4689(6), Aug. 2020. [link] 

35. D. Kim, C. Park, W. Choi, S.-H. Shin, B. Jin, R.-H. Back, and J.-S. Lee*, “Improved Long-Term Responses of Au-Decorated Si Nanowire FET Sensor for NH3 Detection”, IEEE SENSORS JOURNAL, vol. 20, no. 5, pp. 2270–2277, Mar. 2020. [link]

34. S. Lee, J.-S. Yoon, J. Jeong, J. Lee, and R.-H. Baek*, "Observation of mobility and velocity behaviors in ultra-scaled LG = 15 nm silicon nanowire field-effect transistors with different channel diameters", Solid-State Electronics, vol. 164, pp. 107704-1~5, Feb. 2020. [link]

33. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek*, “Sensitivity of Source/Drain Critical Dimension Variations for Sub-5-nm Node Fin and Nanosheet FETs,” IEEE Trans. on Electron Devices, vol. 67, no.1, pp. 258-262, Jan. 2020. [link]

International Journals (*corresponding)

32. G. Kang, J.-S. Yoon, G.-W. Kim, K. Choi, T. Park*, R.-H. Baek*, and J. Lim*, "Electron trapping and extraction kinetics on carrier diffusion in metal halide perovskite thin films", Journal of Materials Chemistry A, vol. 7, no. 45, pp. 25838 - 25844, Dec. 2019. [link]

31. J.-S. Yoon, S. Lee, J. Lee, J. Jeong, H. Yun, B. Kang, and R.-H. Baek*, “Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node ,” IEEE Access, vol. 7, pp. 172290 - 172295, Nov. 2019. [link]

30. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek*, “Bottom oxide bulk FinFETs without Punch-through-stopper for extending toward 5-nm node,” IEEE Access, vol. 7, pp. 75762 - 75767, June. 2019. [link]

29. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek*, “Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications” Japanese Journal of Applied Physics, vol. 58, no. SB, pp. SBBA12-1~5, Apr. 2019. [link]

28. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek*, “Metal Source-/Drain-Induced Performance Boosting of Sub-7-nm Node Nanosheet FETs,” IEEE Trans. on Electron Devices, vol. 66, no.4, pp. 1868-1873, Apr. 2019. [link]

27. J.-S. Yoon, J. Jeong, S. Lee, and R.-H Baek*, “Punch-through-stopper Free Nanosheet FETs with Crescent Inner-spacer and Isolated Source/Drain,” IEEE Access, vol. 7, no.1, pp. 38593-38596, Mar. 2019. [link]

International Journals (*corresponding)

26. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek*, "Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs,” IEEE Journal of the Electron Devices Society, vol. 6, pp. 942-947, Aug. 2018. [link]

25. J.-S. Yoon, J. Jeong, S. Lee, and R.-H. Baek*, "Multi-Vth Strategies of 7-nm node Nanosheet FETs with Limited Nanosheet Spacing,” IEEE Journal of the Electron Devices Society, vol. 6(1), pp. 861-865, Jul. 2018. [link]

24. J.-Y. Lee, H. Lee, B. Jin, H. Oh, S. Baek, G. Yoon, Y. Lee, R.-H. Baek, and J.-S. Lee*, "Impact of Geometrical Parameters on the Electrical Performance of Network-Channel Polysilicon Thin-Film Transistors,” Japanese Journal of Applied Physics, vol. 57, no. 10, pp. 104001-1~5, Oct. 2018. [link]

23. J.-S. Yoon, and R.-H. Baek*, "Study on Random Dopant Fluctuation in Core-shell Tunneling Field-effect Transistors,” IEEE Trans. Electron Devices, vol. 65, no.8, pp. 3131-3135, Aug. 2018. [link]

22. H. Oh, J. Kim, R.-H. Baek, and J.-S. Lee*, “Threshold voltage variation depending on single grain boundary and stored charges in an adjacent cell for vertical silicon-oxide-nitride-oxide-silicon (SONOS) NAND flash memory,” Japanese Journal of Applied Physics, vol. 57, no. 4S, pp. 04FE17-1~5, Apr. 2018. [link]

21. J. Kim, H. Oh, Bo Jin, R.-H. Baek, and J.-S. Lee*, "Analog Figure-of-merits Comparison of Gate Workfunction Variability and Random Discrete Dopant between Inversion-mode and Junctionless Nanowire FETs", Journal of Nanoscience and Nanotechnology, vol.18, no. 9, pp. 6598-6601, Sep. 2018. [link] 

20. S. Baek, J. Lee, I. Park, R.-H. Baek, and J.-S. Lee, "Systematic analysis of oxide trap distribution of 4H-SiC DMOSFETs using TSCIS and its correlation with BTI and SILC behavior", Solid-State Electronics, vol. 140, pp.18-22, Feb. 2018. [link]

International Journals (*corresponding)

19. J. Kim, H. Oh, J. Kim, R.-H. Baek, J.-W. Han, M. Meyyappan, and J.-S. Lee*, "Work Function Consideration in Vaccum Field Emission Transistor Design", Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol. 35, 062203, Nov. 2017. [link] 

18. J.-S.Yoon, C.-K. Baek, and R.-H. Baek*, "Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics,” IEEE Trans. Electron Devices, vol. 63, no. 9, pp. 3399-3405, Sept. 2016. [link]

17. R.-H. Baek, J. S. Kim, D.-K. Kim, T.-W. Kim, and D.-H. Kim, "High-Performance Logic Transistor DC Benchmarking Toward 7 nm Technology-Node Between III-V and Si Tri-gate n-MOSFETs Using Virtual-Source Injection Velocity Model," Solid-State Electronics, vol. 116, pp. 100-103, Feb. 2016. [link]

16. J.-S. Yoon, E.-Y. Jeong, C.-K. Baek, Y.-R. Kim, J.-H. Hong, J.-S. Lee, R.-H. Baek, and Y.-H. Jeong*, "Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node," IEEE Electron Device Lett., vol. 36, no. 10, pp.994-996, Oct. 2015. [link]

15. E.-Y. Jeong, J.-S.Yoon, C.-K. Baek, Y.-R. Kim, J.-H. Hong, J.-S.Lee, R.-H. Baek, and Y.-H. Jeong*, "Investigation of RC Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications,” IEEE Trans. Electron Devices, vol. 62, no. 10, pp. 3441-3444, Oct. 2015. [link]

14. J. H. Hong, S. H. Lee, Y. R. Kim, E. Y. Jeong, J. S. Yoon, J. S. Lee, R.-H. Baek, and Y.-H. Jeong*, “Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs,” Japanese Journal of Applied Physics, vol. 54, no. 4S, pp. 04DN05-1~5, Apr. 2015. [link]

13. E.-Y. Jeong, M. J. Deen, C.-H. Chen, R.-H. Baek, J.-S. Lee, and Y.-H. Jeong*, “Physical DC and Thermal Noise Models of 18 nm Double-Gate Junctionless pMOSFETs for Low Noise RF Applications,” Japanese Journal of Applied Physics, vol. 54, pp. 04DC08-1~6, Apr. 2015. [link]

12. R.-H. Baek, C. Y. Kang, C.-W. Sohn, Dae M. Kim, and P. D. Kirsch*, "Investigation of Process-Induced Performance Variability and Optimization of the 10 nm Technology Node Si Bulk FinFETs," Solid-State Electronics, vol. 96, pp. 27-33, June, 2014. [link]

11. K. Majumdar, S. Vivekanand, C. Huffman, K. Matthews, T. Ngai, C. H. Chen, R.-H. Baek, W. Y. Loh, M. Rodgers, H. Stamper, S. Gausepohl, C. Y. Kang, C. Hobbs, and P. D. Kirsch*, "STLM: A Sidewll TLM Strucutre for Accurate Extraction of Ultralow Specific Contact Resistivity," IEEE Electron Device Lett., vol. 34, no.9, pp.1082-1084, Sep. 2013. [link]

10. C.-W. Sohn, C. Y. Kang, R.-H. Baek, D.-Y, Choi, H. C. Sagong, E.-Y. Jeong, C.-K. Baek, J.-S. Lee, Lee. J. C, and Y.-H. Jeong*, “Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications,” IEEE Electron Device Lett., vol. 33, no. 9, no.9, pp.1234-1236, Sep. 2012. [link]

9. C. H. Park, M. D. Ko, K. H. Kim, R.-H. Baek, C. W. Sohn, C. K. Baek, S. Park, M. J. Deen, Y. H. Jeong, and J. S. Lee*, "Electrical characteristics of 20-nm junctionless Si nanowire transistors," Solid-State Electronics, vol. 73, pp. 7-10, Jul. 2012. [link]

8. R.-H. Baek, C. K. Baek, H.-S. Choi, J.-S. Lee, Y. Y. Yeoh, K. H. Yeo, D.-W. Kim, Kinam Kim, Dae M. Kim, and Y. H. Jeong*, “Characterization and modeling of 1/f noise in Si-nanowire FETs: effect of cylindrical geometry and different processing of oxides,” IEEE Trans. Nanotechnol., vol. 10, no. 3, pp. 417-423, May. 2011. [link]

7. R.-H. Baek, C.-K. Baek, S.-H. Lee, S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Yeo, D.-W Kim, J.-S. Lee, Dae M. Kim, and Y. H. Jeong*, "C-V Characteristics in Undoped Gate-All-Around Nanowire FET Array," IEEE Electron Dev., Lett., vol. 32, no. 2, pp. 116-118, Feb. 2011. [link]

6. R.-H. Baek, C. K. Baek, S.-W. Jung, Y. Y. Yeoh, D.-W. Kim, J.-S. Lee, Dae M. Kim, and Y. H. Jeong*, “Characteristics of the Series Resistance Extracted from Si Nanowire FETs Using the Y-Function Technique,” IEEE Trans. Nanotechnol., vol. 9, no. 2, pp. 212-217, Mar, 2010. [link]

5. R.-H. Baek, C. K. Baek, S. W. Jung, Y. Y. Yeoh, D. W. Kim, J. S. Lee, D. M. Kim, and Y. H. Jeong*, "Comparison of Series Resistance and Mobility Degradation Extracted from n- and p-Type Si-Nanowire Field Effect Transistors Using the Y-Function Technique," Japanese Journal of Applied Physics, vol. 49, pp. 04DN06-1~5, Apr. 2010. [link]

4. S. H. Song, H.-S. Choi, R.-H. Baek, G.-B. Choi, M.-S. Park, K. T. Lee, H. C. Sagong, S.-H. Lee, S. W. Jung, C. Y. Kang, and Y.-H. Jeong*,  “A new physical 1/f noise model for double stack high-k gate dielectric MOSFETs,” IEEE Electron Device Lett., vol. 30, No. 12, pp. 1365-1367, Dec. 2009. [link] 

3. H. S. Choi, S. H. Hong, R.-H. Baek, K. T. Lee, C. Y. Kang, R. Jammy, B. H. Lee, S. W. Jung, and Y. H. Jeong*, "Low-Frequency Noise After Channel Soft Oxide Breakdown in HfLaSiO Gate Dielectric," IEEE Electron Device Lett., vol. 30, no. 5, pp. 523-525, May 2009. [link] 

2. K. T. Lee, C.Y. Kang, H-S. Choi, S-H. Hong, G-B. Choi, J.C. Kim, S-H. Song, R.-H. Baek, M-S. Park, H.C. Sagong, B.H. Lee, G. Bersuker, H-H. Tseng, R. Jammy, Y-H. Jeong*, “A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 Gate Stack nMOSFETs”, Microelecton. Eng., vol. 88(12), pp. 3411-3414, Dec. 2011. [link] 

1. S. H. Hong, G. B. Choi, R.-H. Baek, H. S. Kang, S. W. Jung, and Y. H. Jeong*, "Low-temperature performance of nanoscale MOSFET for deep-space RF applications," IEEE Electron Device Lett., vol. 29, no. 7, pp. 775-777, Jul 2008. [link]